Resume of Meenakshi Balakrishnan
Updated: 18th Nov 2020
Name: M. Balakrishnan
Date of
birth: 28th Aug. 1956
Address for
correspondence:
Postal address: 8,
West Avenue, IIT Campus, New Delhi 110016
Email: mbala@cse.iitd.ac.in
Telephone: 9871666611
Field(s) of specialization:
Assistive
devices for the visually impaired
Embedded
system design
Behavioral
and system level synthesis
System level
design & modeling
Hardware-software
codesign
Computer
architecture
Academic
qualifications:
Ph.D.(EE) 1984 IIT Delhi
Thesis title : A
Microprogram Generating system with Emphasis on Signal Processing
Architectures)
B.E.(Hons.)(EEE) 1977 BITS,Pilani First rank
in Engg. in 1977(CGPA : 9.77)
Positions held, Date of joining
and the Institution (In reverse chronological order):
Position Period Place
Professor Aug'97
– present Dept.
of CSE, IIT Delhi
(On leave from 1st Jan 2020)
Vice Chancellor Jan’20
– Sep’20 Satya
Bharti Institute of Technology
Deputy Director Jul’16
– Sep’19 IIT
Delhi
(Strategy & Planning)
Coordinator, School of IT Jul’15
– Aug’16 ANSK
School of IT, IIT Delhi
Deputy Director(Faculty) Jul’09
– Jun’12 IIT
Delhi
Dean(PGS&R) Sep'06
– Aug‘09 IIT
Delhi
Head Sep'01
- Aug'04 Dept.
of CSE, IIT Delhi
Visiting Prof. Aug'94
- Jul'95 LS
Informatik XII, Univ. of Dortmund
Associate Prof. Apr'91
- July'97 Dept.
of CSE, IIT Delhi
Assistant Prof. Dec'88
- Mar'91 Dept.
of CSE, IIT Delhi
Visiting Scientist May'88
- Dec'88 Institut
fuer Informatik, Univ. of Kiel
Assistant Prof. Sep'87
- May'88 Dept.
of ECE, Syracuse Univ.
Research Associate Sep'85
- Aug'87 Dept.
of CIS, Univ. of Guelph
Scientist May'77
- Aug'85 CARE,
IIT Delhi
Awards and fellowships
Award (Body) |
Year |
Details |
Life Time
Award (IIT Delhi) |
2020 |
IIT Delhi
– Given to one senior faculty each year |
Eugene L
Lawler Award (ACM)* |
2019 |
Humanitarian
Contributions within Computer Science and Informatics (Once in 2 years) |
Fellow
(INAE) |
2018 |
Fellow of
the Indian National Academy of Engineers |
National
Award (DST) |
2018 |
RBD-
Scientist impacting life of the Disabled |
National
Award (DST) |
2016 |
OnBoard -
Scientist impacting life of the Disabled |
Manthan
Award (DEF) |
2015 |
SmartCaneTM
- - Scientist impacting life of the Disabled |
National
Award (MSJE) |
2015 |
SmartCaneTM
– Research impacting life of the Disabled (Given to the parent
Department) |
NCPEDP-Mphasis
Universal Design |
2015 |
Working
Professionals |
IIT Delhi
Golden Jubilee Committee (IIT Delhi) |
2010 |
Mentor
Award – 20 Alumni nominate a teacher for the award |
Vasvik
Award 2005 |
2008 |
Research
that is industrially relevant |
TODAES
2007 Best paper Award* |
2007 |
SIGDA
(given at DAC 2007) |
Konrad
Zuse fellow (DAAD)* |
1994 |
DAAD
Germany gives to one Computer Science visiting Professor each year |
Invention
Award (NRDC) |
1982 |
NRDC
invention award for the work of Deck Landing Mirror Sight |
Silver Medal
(BITS Pilani) |
1977 |
I in Engg. 1977 and II among the batch
of 1972 |
NSTS
Scholarship (NCERT and IARI) |
1972 |
IARI gave the fellowship for studying
Agri. Engg. - Not accepted |
Best School
Boy Award (Birla Higher Secondary School) |
1972 |
Annually
one student in the graduating class is selected as Best School Boy |
*International awards
Professional Achievements and contributions:
·
31 journal, 106
refereed conference publications, two books, two book chapters, seven patents
including two PCTs, one trademark and one design registration (List of publications in Annexures A, B,
C and D)
·
32 sponsored
research projects (approx. Rs. 15.00 crores) with PI in 18 of them (approx. Rs 10.00
crores) . Apart from that 21 consultancies including from leading EDA/VLSI
companies (Annexure E)
·
17 PhDs and 4
MS(R) completed with 5 PhDs (including 1 submitted) and 1 MS(R) ongoing
(Annexure F)
·
129 MTechs
and 87 BTech projects supervised till July 2020 (List on my homepage –
www.cse.iitd.ac.in/~mbala)
·
Founding
member of 3 start-ups (Annexure G)
·
Responsible
for 6 technology transfers (Annexure H)
·
Many
significant contributions to technical activities and professional societies
(Annexure I)
·
Key initiatives
and contributions in education and research management at IIT Delhi (Annexure
J)
·
Key
Initiatives and contributions in Embedded/VLSI/EDA/CS domains (Annexure K)
·
Academic
planning for establishment of Satya Bharti Institute of Technology (Annexure L)
Key Outside IIT Delhi Memberships and Roles:
·
Educational
Institutions
-
Member,
BoG, NSIT Delhi (2005 - 2016)
-
Member, Academic Council, SMVDU, Jammu
(2006 - 2014)
-
Member,
Advisory role of Indraprastha Institute of Information Technology (IIIT) Delhi
(2008 - 2011)
-
Alumni
advisory committee, BITS Pilani, (2011 - 2014)
-
Member,
Academic Council, JNU (2012 - 2015)
-
Member, BoG,
NIT Delhi (2019 - )
-
Member,
Senate IIIT Sri City (2019 - )
·
Industry/Industry
bodies
-
Chairman,
Board of Directors, KritiKal Solutions India (Pvt) Ltd. TBIU Startup (2006 -
2013)
-
Director
(Non-executive), TCIL (2009 - 2013)
-
Director
(Non-executive), ITI (2009 - 2013)
-
Member,
Education Core Group, FICCI (2020 - )
-
Member,
Education Council, CII (2020 - )
·
Professional
-
Steering
Committee Member, VLSI Design (2006 - 2015)
-
ACM DSP
Committee, ACM New York (2011 – 2015)
-
Member,
Research Advisory Council, CEERI, Pilani (CSIR laboratory) (2010 - 2016)
-
Member,
Industrial Applications WG, MCIT, Govt.
of India (2010 - 2013 )
-
Member,
Microelectronics WG, MCIT, Govt. of
India (2010 - 2013)
-
Senior
Member, IEEE
-
Senior
Member, ACM
-
Founding
Member, ACM India Council (2009- 2012)
-
President,
ACM NCR Chapter (2011-2015)
-
Associate
Editor, IEEE Embedded Systems Letters (ESL) (2013 - 2016)
-
Associate
Editor, ACM TECS (2017 - )
Referees (detailed office/residence addresses
or phone numbers on request):
Within IIT Delhi
Prof. Ramgopal
Rao, Director, IIT Delhi, New Delhi, 110016
(rrao@admin.iitd.ac.in)
Prof.
Surendra Prasad, ex-Director, IIT Delhi, New Delhi, 110016
(sprasad.iitd@gmail.com)
Prof. Anshul
Kumar, Professor, CSE Department, IIT Delhi, New Delhi, 110016
Outside IIT Delhi Within India
Prof. S.N.
Maheshwari, Retd Professor, CSE, IIT Delhi, New Delhi 110016
(snm@cse.iitd.ac.in)
Prof. B.N.
Jain, Ex-VC, BITS Pilani, Ex-DD(F), IIT Delhi
(bnjain@cse.iitd.ac.in)
Mr. V.B.
Taneja, Retired Senior Director, MCIT, New Delhi
Outside India
Prof. Sharad
Malik, Department of Electrical Engineering, Princeton University, USA
Prof. Peter
Marwedel, Department of Computer Science, University of Dortmund, Germany
Prof.
Vishwani Agrawal, Auburn University, USA
Prof. Nikil
Dutt, Department of Computer Science, University of California, USA
Annexure A
Complete list of publications in
standard refereed journals
1. Solomon Abera, M Balakrishnan and Anshul Kumar, “Performance-Energy Trade-off in Modern CMPs”, accepted for publication as full paper in ACM Transactions on Architecture and Code Optimization
2.
R Devadoss, K Paul, M Balakrishnan, “Equivalence
Checking and Compaction of n-input Majority Terms Using Implicants of Majority”, Journal
of Electronic Testing 35 (5), Springer, Oct 2019, pp. 679-694
3.
G Ananthanarayanan,
SR Sarangi, M Balakrishnan , “Task Assignment Algorithms for Multicore
Platforms with Process Variations”, Journal of Low Power Electronics 14
(2), June 2018, pp. 302-317
4.
R Gupta, PVM Rao, M Balakrishnan, S Mannheimer, Basic Identity
Tags (BITs) in Tactile Perception of 2D shape, The Journal on Technology and
Persons with Disabilities, Mar 2018, , pp. 103 – 116
5.
Mansureh
Shahraki Moghaddam, M Balakrishnan and Kiyoung Choi, “Optimal mapping of
program overlays onto many-core platforms with limited memory capacity”,
Design Automation for Embedded Systems, Springer U, Dec 2017, Vol 21, No. 3-4,
pp. 173-194
6.
Piyush
Chanana, Rohan Paul, M Balakrishnan, PVM Rao, “Assistive technology
solutions for aiding travel of pedestrians with visual impairment”, Journal of Rehabilitation and Assistive
Technologies Engineering, SAGE Publications, vol. 4, Aug 2017, pp.
2055668317725993
7.
B Sharat
Chandra Varma, Kolin Paul, M Balakrishnan, Dominique Lavenier, “Hardware
acceleration of de novo genome assembly”, International Journal of
Embedded Systems, Inderscience Publishers (IEL), Vol. 9, Issue 1, 2017, pp.
74-89
8.
Richa Gupta,
M Balakrishnan, PVM Rao, “Tactile Diagrams for the Visually
Impaired”, IEEE Potentials, IEEE, Jan 2017, Vol 36, No. 1, pp. 14-18
9.
Manish Kumar
Jaiswal, B. Sharat Chandra Verma, Hayden K.-H. So, M. Balakrishnan, Kolin Paul,
Ray C.C. Cheung, “Configurable
Architectures for Multi-Mode Floating Point Adders”, IEEE Trans. On
Circuits and Systems I, Vol 62(8), 2079-2090, 2015
10.
Arun Kumar
Parakh, M. Balakrishnan and Kolin Paul, “Improving Map-Reduce for GPUs
with cache”, Int. J. High Performance Systems Architecture, Vol. 5, No.
3, 2015, pp. 166-177
11.
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, “Series Expansion based
Efficient Architectures for Double Precision Floating Point
Division”, Circuits Systems and
Signal Processing, vol. 33, No. 11, 2014, pp. 3499-3526
12.
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, “Unified Architecture for
Double/Two-Parallel Single Precision Floating Point Adder”, IEEE Trans. on
Circuits and Systems Vol. 61-II,
No. 7, 2014,
pp. 521-525
13.
Gayathri
Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, and Smruti R. Sarangi,
“Amdahl's Law in the Era of Process Variation”, Vol. 4, No. 4, 2013, International Journal of
High Performance Systems Architecture (IJHPSA), pp. 218-230
14.
Sonali
Chouhan, M. Balakrishnan, Ranjan Bose, "System-Level Design Space
Exploration Methodology for Energy-Efficient Sensor Node Configurations: An
Experimental Validation", IEEE Trans. on CAD of Integrated Circuits and
Systems, Vol. 31, No.4, 2012, pp. 586-596
15.
Rajeswari
Devadoss, Kolin Paul, M. Balakrishnan, "p-QCA: A Tiled Programmable Fabric
Architecture Using Molecular Quantum-Dot Cellular Automata", JETC, Vol. 7,
No. 3, 2011, Article No. 13
16.
P Panda, M
Balakrishnan and A. Vishnoi, “Compressing Cache
State for Post-Silicon Processor Debug” IEEE Transactions on Computers, Vol. 60,
No. 4, April 2011, pp
484-497
17.
R. Devadoss,
K. Paul, M. Balakrishnan, “Coplanar QCA crossovers”, Electronics
Letters, Volume 45, Issue 24, November 19 2009, pp.1234 –
1235
18.
Sonali
Chouhan, Ranjan Bose, M. Balakrishnan, “Integrated Energy Analysis of
Error Correcting Codes and Modulation for Energy Efficient Wireless Sensor
Nodes”, IEEE Transactions on Wireless
Communications, Volume
8, Issue 10, October 2009, pp. 5348 -
5355
19.
Sonali
Chouhan, Ranjan Bose, M. Balakrishnan, “A Framework for Energy
Consumption Based Design Space Exploration for Wireless Sensor Nodes”,
IEEE Trans. on CAD of Integrated Circuits and Systems, Volume 28, Issue 7, July 2009, pp. 1017 -
1024
20.
Anup
Gangwar, M. Balakrishnan, Anshul Kumar and Preeti Ranjan Panda, ``Evaluation of
Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'',
International Journal of Parallel Programming (IJPP), Springer, The
Netherlands, vol 35, pp. 507-527, Dec 2007
21.
Anup Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of
Inter-cluster Mechanisms on ILP in Clustered VLIW Architectures'', ACM TODAES,
Vol. 12, No. 1, Jan 2007, pp. 1-29. (Best Paper Award for ACM TODAES
2007)
22.
Manoj Kumar
Jain, M. Balakrishnan and Anshul Kumar, ``Efficient Technique for Exploring
Register File SIze in ASIP Design'', IEEE Trans. on VLSI, vol. 23, No. 12, pp. 1693-1699,
Dec. 2004.
23.
L. Wehmeyer,
Manoj Jain, Stefan Steinke, Peter Marwedel and M. Balakrishnan, "Analysis
of the Influence of Register File Size on Energy Consumption, Code Size and
Execution Time" IEEE Trans. on CAD of Integrated Circuits and Systems,
vol. 20, no. 11, Nov. 2001, pp. 1329-1337.
24.
M.
Balakrishnan and Heman Khanna, ``Allocation of FIFO Structures in RTL Data
Paths", ACM TODAES, July 2000, pp. 294-310.
25.
A.R. Naseer,
M. Balakrishnan and Anshul Kumar, ``Direct Mapping of RTL Structures onto LUT
based FPGAs'', IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 17,
No. 7, July 1998, pp. 624-631
26.
Alok
Mittal,Aditya Vailaya, S, Banerjee and M. Balakrishnan, "Real Time Vision
System for Collision Detection" CSI Journal of Computer Science and
Informatics, March 1995, pp. 13-29. (Best Paper Award of CSI Journal of
Computer Science and Informatics 1995)
27.
M.Balakrishnan,
A.K.Majumdar, D.K.Banerji and J.G.Linders, "Synthesis of Decentralized
Controllers from High Level Description", Euromicro Journal of
Microprocessing and Microprogramming, Vol. 22, No. 3, May 1988, pp 217-229.
28.
M.Balakrishnan,
A.K.Majumdar, D.K.Banerji, J.G.Linders and J.C.Majithia, "Allocation of
Multiport Memories in Data Path Synthesis", IEEE Trans. on CAD of
Integrated Circuits and Systems, vol 7, April 1988, pp 536-540.
29.
M.Balakrishnan,
A.K.Majumdar, D.K.Banerji, J.G.Linders and J.C.Majithia, "A Semantic
Approach to Modular Synthesis of VLSI Systems", Information Processing
Letters, Vol 27, No. 1, Feb. 1988, pp 1-7.
30.
M.Balakrishnan,
B.B.Madan and P.C.P.Bhatt, "An Efficient Retargetable Micro-code
Generating System", Euromicro Journal of Microprocessing and
Microprogramming, Vol. 19, No. 4, Oct. 1987, pp 305-318.
31.
M.Balakrishnan,
P.C.P.Bhatt and B.B.Madan, "A Survey of Microprogramming Languages",
Euromicro Journal of Microprocessing and Microprogramming, Vol. 17, No. 1, Jan.
1986, pp 19-27.
Annexure B
Complete list of papers published
in peer reviewed conferences
1. Akashdeep,
M Balakrishnanm Volker Sorge, “Evaluating Cognitive Complexity of
Algebraic Equations”, Accepted for presentation in 36th CSUN Conference, March
2021
2. Shikha
Goel, Rajesh Kedia, M. Balakrishnan and Rijurekha Sen, "INFER:
INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on
DPUs", Accepted for presentation at FPT 2020, 9-11 Dec. 2020, Maui,
Hawaii, USA
3. Rajesh
Kedia, M. Balakrishnan, and Kolin Paul, Work-in-Progress: A case for design space
exploration of context-aware adaptive embedded systems, CODES+ISSS, Oct. 2019
4. Anupam
Sobti, M. Balakrishnan and Chetan Arora, Multi-sensor Energy Efficient Obstacle
Detection, Euromicro DSD 2019, Chalkidiki, Greece, 28-30 Aug 2019, pp 19-26
5. Rajesh Kedia,
M. Balakrishnan and Kolin Paul "GRanDE: Graphical representation and
design space exploration of embedded systems", Euromicro DSD 2019, Chalkidiki, Greece,
28-30 Aug 2019, pp 4-12
6.
R Gupta, PVM Rao, M Balakrishnan, S Mannheimer, Evaluating the Use
of Variable Height in Tactile Graphics, 2019 IEEE World Haptics Conference
(WHC), Montreal, Canada, 3-6 July 2019, pp. 121-126
7.
S Holani, A Bansal, M Balakrishnan, Pushpak: Voice Command-based
eBook Navigator, Proceedings of the 16th Web For All, May 2019
8.
SP Chowdhary, D Manocha, M Balakrishnan, A Bansal, H Garg,
Making Legacy Digital Content Accessible at Source, Proceedings of the 16th Web
For All, May 2019
9.
SA Bekele, M Balakrishnan, A Kumar, ML guided energy-performance
trade-off estimation for uncore frequency scaling, 2019 Spring Simulation
Conference (SpringSim), 1, 2019
10. R
Devadoss, K Paul, M Balakrishnan, Majority Logic: Prime Implicants and n-Input
Majority Term Equivalence , 32nd International Conference on VLSI Design, Jan 2019
11. SM
Adhepalli, P Sapra, S Agrawal, P Chanana, M Balakrishnan, FPGA-Based
Controllers for Compact Low Power Refreshable Braille Display, IEEE Computer Society Annual Symposium
on VLSI (ISVLSI), 632-637, July 2018
12. Manshul
Belani, Dinesh Kaushal, Manish Agrawal and M Balakrishnan, “DescribeIt: CSUN 2018, March 2018, San Diego
13. Richa
Gupta, Steven Mannheimer, M Balakrishnan and PVM Rao, “Basic Identity
Tags (BITs) in tactile perception of 2D shape”, (accepted for
presentation)
14. Anupam
Sobti, Chetan Arora and M. Balakrishnan, “Object Detection in Real-Time
Systems: Going Beyond Precision”, WACV 2018, March 2018, Lake Tahoe, USA pp.
1020-1028
15. Solomon
Abera Bekele, M. Balakrishnan and Anshul Kumar, “Performance-Energy
Trade-off in CMPs with Per-Core DVFS”, April 2018, International
Conference on Architecture of Computing Systems, Braunschweig, Springer, Cham ,
pp 225-238
16. Varan
Gupta, Pulkit Sapra, Suman Muralikrishnan, M Balakrishnan, PVM Rao, “Design
and Comparative Analysis of Linear Guides for Refreshable Braille Displays”,
Aug 2017, ASME 2017 IDETC&CIE, Cleveland, DETC2017-68308, pp.
V05BT08A030-V05BT08A030
17. Pulkit
Sapra, Ankit Kumar Parsurampuria, Suman Muralikrishnan, Varan Gupta, H
Karthikeyan, K Bhagavatheesh, Arun Venkatesan, Sashikumar Valiyaveetil, M Balakrishnan,
PVM Rao,”Refreshable Braille Display Using Shape Memory Alloy With Latch
Mechanism”, Aug 2017, ASME 2017 IDETC&CIE, Cleveland, DETC2017-68311,
pp. V009T07A040-V009T07A040 (Best Paper Award)
18. Solomon
Abera, M Balakrishnan, Anshul Kumar, “PLSS: A Scheduler for Multi-core
Embedded Systems”, April 2017, International Conference on Architecture
of Computing Systems, Vienna, Springer, Cham, pp. 164-176
19. Rajesh
Kedia, KK Yoosuf, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, M
Balakrishnan, “MAVI: An Embedded Device to Assist Mobility of Visually
Impaired”, 30th International Conference on VLSI Design and 2017 16th
International Conference on Embedded Systems (VLSID), 2017, Hyderabad, India,
IEEE, Jan 2017, pp. 213-218
20. G
Ananthanarayanan, SR Sarangi, M Balakrishnan, “Leakage Power Aware Task
Assignment Algorithms for Multicore Platforms”, VLSI (ISVLSI), 2016 IEEE
Computer Society Annual Symposium on VLSI, 11-13 July, Pittsburg, USA, 607-612
21. Kunal
Kwatra, Renu Kaushik, Lipika Vidawat, Vibha Choudhary, Mayank Aamseek,
Kameshwar Chesetti, M. Balakrishnan, “Converting Mathematics Textbook to
Tactile Form: Process and Experiences”, DEIMS 2016, Kanagawa , Japan, 4-6
Feb 2016
22. Siddhartha
Gupta, Manshul V Belani, Dinesh Kaushal, M. Balakrishnan, “Microsoft
Excel ChartsTMAccessibility: An Affordable and Effective Solution”, DEIMS
2016, Kanagawa , Japan, 4-6 Feb 2016
23.
Pulkit
Sapra, Ankit Kumar Parsurampuria, Dhruv Gupta, Suman Muralikrishnan, Mayank
Raj, Akash Anand, Vinit Darda,” Rohan Paul, M Balakrishnan and P.V.M.
Rao, “A Compliant Mechanism Design for Refreshable Braille Display Using
Shape Memory Alloy”, ASME – MESA 2015, 2-5 Aug 2015, Boston, USA
24.
Dheeraj
Mehra, Deepak Gupta, Vishwarath.T, Neil Shah, Piyush Chanana, Siddharth, Rohan
Paul, BalaKrishnan M and PVM Rao, "Bus Identification System for
Visually Impaired: Evaluation and learning from field trials", Accepted
for presentation at TRANSED 2015, 29-31 July 2015, Lisbon, Portugal
25.
Rajeswari
Devadoss, Kolin Paul and M Balakrishnan, “MajSynth : An n-input Majority
Algebra based Logic Synthesis Tool for Quantum-dot Cellular Automata”, 22nd
Intl. Workshop on Logic Synthesis, 12-13 June 2015, Mountain View, California
26.
Mansureh Shahraki
Moghaddam, M.
Balakrishnan, Kolin Paul, “Partial Reconfiguration
for Dynamic Mapping of Task Graphs onto 2D Mesh Platform”, ARC 2015, 13-17 April, 2015, Bochum,
Germany, pp. 373-382
27.
B. Sharat Chandra
Varma, Kolin Paul, M. Balakrishnan, “High
Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs” DSD 2014, 27-29 Aug., Verona, Italy, pp.
66-73
28.
Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan,
“Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant
Tactile Graphics for Science and Mathematics.”, ICCHP (2), 7-11
July, 2014, Paris, France, pp.
34-41
29.
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, “Configurable
Architecture for Double/Two-Parallel Single Precision Floating Point
Division”, ISVLSI 2014, 2-9 July 2014, Tampa, Florida,
pp. 332-33
30.
Mansureh Shahraki
Moghaddam, Kolin Paul, M. Balakrishnan, “Mapping
Tasks to a Dynamically Reconfigurable Coarse Grained Array”, (Poster paper) FCCM 2014, 11-13 May, Boston, pp 33
31.
Smruti R.
Sarangi, Gayathri Ananthanarayanan, and M. Balakrishnan, “LightSim : A
Leakage Aware Ultrafast Temperature Simulator”, 19th ASP-DAC,
20-23 Jan 2014, Singapore, pp. 855-860
32.
B. Sharat
Chandra Varma, Kolin Paul, M. Balakrishnan, "Accelerating Genome
Assembly using Hard Embedded Blocks in FPGAs.",
IEEE 27th International Conference on VLSI Design, 5-9 Jan 2014, Mumbai,
pp. 306-311
33.
Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika, M. Balakrishnan: A
path-guided audio based indoor navigation system for persons with visual
impairment, ASSETS '13,
October 21-23 October, 2013, Bellevue, WA, USA, pp. 33.
34.
Mansureh S,
Kolin Paul and M Balakrishnan, "Design and Implementation of High
Performance Architectures with Partially Reconfigurable CGRAs" 20th
Reconfigurable Architectures Workshop (RAW 2013), May 20-21, 2013, Boston, USA
35.
B. Sharat Chandra
Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier, “ FAssem: FPGA Based
Acceleration of De Novo Genome Assembly”, FCCM 2013, 28-30 April, Seattle, USA, pp. 173-176
36.
Lava
Bhargava, Ranjan Bose, M. Balakrishnan, “Novel Hardware Implementation of
LLR-based Non-binary LDPC Decoders’, NCC 2013, New Delhi, Feb 2013
37.
Arun Kumar
Parakh, M. Balakrishnan, Kolin Paul, “Performance enhancement of
Map-Reduce framework on GPU”,
The 11th IASTED International Conference on Parallel and Distributed
Computing and Networks (PDCN 2013), Feb 2013, Innsbruck, Austria
38.
Dheeraj
Mehra, M. Balakrishnan et.al., “Design for user testing of
affordable bus identification and homing system for the visually
impaired”, Presented at Transportation Research Board Annual Conference
(TRB 2013), Washington D.C. USA, Jan 2013
(selected for presentation in a special session at TRB 2013 from TRANSED
2012), Proc. of 13th International conference on Mobility and Transport
for Elderly and Disabled Persons (TRANSED 2012), Sep. 2012, New Delhi, India
39.
Sharat
Chandra Verma, Kolin Paul, M Balakrishnan, “Accelerating 3D-FFT using
Hard Embedded Blocks in FPGA”, 23rd Proceedings of the International Conference on
VLSI Design, Pune,
India, Jan. 2013
40.
Dhruv Jain, M.
Balakrishnan et.al. “Design and user
testing of an affordable cell phone based indoor navigation system for visually
impaired”,
Proc. of 13th International conference on Mobility and Transport for Elderly
and Disabled Persons (TRANSED 2012), Sep. 2012, New Delhi, India, Best
Paper Award (http://www.transed2012.in/Best%20Paper%20Awards/M__47)
41.
Arun Kumar
Parakh, M. Balakrishnan, Kolin Paul, “Performance estimation and
application mapping on different GPUs”, 26th IEEE International Parallel
& Distributed Processing Symposium Workshop (IPDPSW2012), May 2012, Shanghai, China
42.
Rajeswari
Devadoss, Kolin Paul, M. Balakrishnan, "Architecture and tools for
programmable QCA", FPT 2011, Dec. 2011, Delhi, pp. 1-4
43.
R. Devadoss,
K. Paul, M. Balakrishnan, “A Tiled Programmable Fabric using
QCA”, FPT 2010, Beijing, Dec.
2010, pp. 9-16
44.
Preeti
Ranjan Panda, Anant Vishnoi and M. Balakrishnan, “Enhancing post-silicon
processor debug with Incremental Cache state Dumping”, IEEE VLSI-SOC,
Madrid, Spain, September 2010, pp. 55-60
45.
Rohan Paul,
M. Balakrishnan et.al. "Smart
Cane for the Visually Impaired" Proc. of 12th International conference on
Mobility and Transport for Elderly and Disabled Persons, (TRANSED 2010), Hong
Kong, June 2010 (Peter Chan Best Paper Award)
46.
Vasudev
Sharma, M. Balakrishnan et.al. “User Triggered Bus Identification and
Homing System: Making Public Transport Accessible for the Visually
Challenged”, Proc. of 12th International conference on Mobility and
Transport for Elderly and Disabled Persons, (TRANSED 2010), Hong Kong, June
2010
47.
R. Devadoss,
K. Paul, M. Balakrishnan,
Clocking-based Coplanar Wire Crossing Scheme for QCA at 23rd Proceedings of the International Conference on
VLSI Design, Bengaluru,
India, Jan. 2010, pp. 339-344
48.
R. Devadoss,
K. Paul, M. Balakrishnan, Clocking-based Coplanar Wire Crossing Scheme for QCA
at 1st International Workshop on Quantum-dot Cellular
Automata, UBC, Vancouver, Canada, Aug. 2009.
49.
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan, “Online
Cache State Dumping for Processor Debug”. DAC 2009, pp. 358-363, Aug. 2009
50.
Sonali Chouhan, M. Balakrishnan, Ranjan Bose, “An Experimental
Validation of System Level Design Space Exploration Methodology for Energy
Efficient Sensor Nodes”, ISLPED 2009, pp. 355-358, Aug. 2009
51.
Anant
Vishnoi, Preeti Ranjan Panda and M.
Balakrishnan, “Cache Aware
Compression for Processor Debug Support” Design Automation and Test in
Europe (DATE), 20-24 April, Nice, France, pp. 208-213, April 2009
52.
Sahu, M.
Balakrishnan and Preeti Ranjan Panda, “A Generic Platform for Estimation
of Multi-threaded Program Performance on Heterogeneous Multiprocessor”,
Design Automation and Test in Europe (DATE) 20-24 April, Nice, France, pp.
1018-1023, April 2009
53.
Kolin
Paul, M. Balakrishnan, Advait Jain,
Pulkit Gambhir and Priyanka Jindal, “FPGA Accelerator for Protein
Structure Prediction Algorithms” SPL 2009, Sao Carlos, Brazil, 1-3 April
2009, pp. 123-128
54.
Sonali
Chouhan, M. Balakrishnan and Ranjan Bose, A Framework for Energy Consumption
Based Design Space Exploration for Wireless Sensor Nodes, In International
Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, pp.
329-334, Aug 2008.
55.
M
Balakrishnan, Kolin Paul, Ankush Garg, Rohan Paul, Dheeraj Mehra, Vaibhav
Singh, P.V.M. Rao, Vishwas Goel, Debraj Chatterjee, Dipendra Manocha, “Cane Mounted Knee-above Obstacle
Detection and Warning System for the visually impaired”, 3rd ASME/IEEE International Conference
on Mechatronic and Embedded Systems and Applications (MESA 2007), Las Vegas,
Nevada, USA, September 2007
56.
Ashutosh Pal
and M. Balakrishnan, ``A Behavioral Synthesis Approach to Distributed Memory
FPGA Architectures'', FPL 2007, Amsterdam, 27- 29 Aug. 2007, pp. 517-520
57.
Rohan Paul,
Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul,
Dipendra Manocha ,``Smart Cane for the Visually Impaired: Technological
Solutions for Detecting Know above Obstacles and Accessing Public Buses'',
Proc. of 11th International conference on Mobility and Transport for Elderly
and Disabled Persons (TRANSED 2007), Montreal, Canada, June 2007
58.
H. Dhand,
Basant Dwivedi and M. Balakrishnan, ``New Approach to Architectural Synthesis:
Incorporating QoS Constraint'', Proc. EMSOFT 2006, Seoul, Korea, Oct. 2006,
pp.301-310.
59.
Basant K.
Dwivedi, Arun Kejariwal, M. Balakrishnan and Anshul Kumar, ``Rapid
Resource-Constrained Hardware Performance Estimation'', Proc. International
Workshop on Rapid System Prototyping (RSP06), Chania, Crete, Greece, June 2006,
pp 40-46.
60.
Akhilesh
Chaudhary, Gaurav Gupta and M Balakrishnan, ``Factoring Large Numbers Using
FPGAs'', Proc of VLSI Design and Test Symposium (VDAT 2005), Bangalore, India,
August 2005
61.
Basant Kumar
Dwivedi, Harsh Dhand, M.Balakrishnan and Anshul Kumar, ``RPNG: A Tool for
Random Process Network Generation'', Proc of Asia and South Pacific
International Conference in Embedded SoCs (ASPICES-2005), Bangalore, India,
July 2005.
62.
Anup
Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar,``Evaluation of
Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'', Proc. of
Design Automation and Test in Europe (DATE05), Munich, Germany, March 2005, pp.
730-735
63.
Ankit
Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, and Subhashis
Banerjee, ``SMPS: An FPGA-based Prototyping Environment for Multiprocessor
Embedded Systems'', IEEE/ACM Thirteenth International Symposium on Field
Programmable Gate Arrays (FPGA-2005), Monterey, USA, February 2005
64.
Manoj Kumar
Jain, M. Balakrishnan and Anshul Kumar, ``Integrated On-chip Storage Evaluation
in ASIP Synthesis'', Proc. 18th International Conference on VLSI Design
(VLSI-2005), Kolkata, India, January 2005, pp 274-279.
65.
Gaurav
Arora, Abhishek Sharma, M. Balakrishnan and D. Nagchoudhuri, ``ADOPT - An
Approach to Activity Based Delay Optimization'', Proc. 18th International
Conference on VLSI Design (VLSI-2005), Kolkata, India, January 2005, pp.
411-416.
66.
Basant Kumar
Dwivedi, Anshul Kumar and M.Balakrishnan, ``Automatic Synthesis of System on
Chip Multiprocessor Architectures for Process Networks '', ISSS 2004, Sep.
8-10, 2004, Stockholm, Sweden, pp. 60-65.
67.
Basant Kumar
Dwivedi, Anshul Kumar and M.Balakrishnan, ``Synthesis of Application Specific Multiprocessor
Architectures for Process Networks'',
Proc. 17th International Conference on VLSI Design, January 2004,
Mumbai, India, pp. 780-787.
68.
Anup
Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of Inter-cluster
Communication Mechanisms on ILP in Clustered VLIW Architectures'', Proc. of the
Workshop on Application Specific Processors (WASP-2, held in conjunction with
MICRO-36), San Diego, USA, Dec. 2003, pp. 56-63.
69.
Manoj Kumar
Jain, M.Balakrishnan and Anshul Kumar, ``Exploring Storage Organization in ASIP
Synthesis'', Euromicro Symposium on Digital System Design (Euro-DSD 2003),
September 2003, Belek Near Antalya, Turkey, pp. 120-127.
70.
Amarjeet
Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi, M. Balakrishnan and
Anshul Kumar "SoC Synthesis with Automatic Interface Generation",
Proc. of 16th International Conference on VLSI Design (VLSI-2003), January
2003, New Delhi, India, pp. 585-590.
71.
Manoj Kumar
Jain, M. Balakrishnan and Anshul Kumar, ``An Efficient Technique for Exploring
Register File Size in ASIP Synthesis", Proc. of CASES 2002, Grenoble,
France, Oct. 2002, pp. 252-261.
72.
C.P. Joshi,
Anshul Kumar and M. Balakrishnan, "A New Performance Evaluation Approach
for System Level Design Space Exploration", Proc. of ISSS02, October 2002,
Kyoto, Japan, pp. 180-185.
73.
Bhuvan
Middha, Varun Raj, Anup Gangwarm Anshul Kumar, M. Balakrishnan and Paolo Ienne,
"A TRIMARAN Based Framework for Exploring the Design Space of VLIW ASIPS
with Coarse Grain Functional Units", Proc. of ISSS02, October 2002, Kyoto,
Japan, pp. 2-7.
74.
Stefan
Steinke, Nils Grunwald, Lars Wehmeyer, Rajeshwari Banakar, M. Balakrishnan and
Peter Marwedel, "Dynamic copying of Instructions into Onchip Memory for
Energy Reduction", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 213-218.
75.
Rajeshwari
Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan and Peter Marwedel,
"Scratchpad Memory: A Design Alternative for Cache On-chip Memory in
Embedded Systems", Proc. of CODES 2002, Estes Park, Colorado, May 2002,
pp. 73-78. (2nd most cited paper published in CODES/ISSS in 10 years;
listed by Frank Vahid and Tony Givargis,
“Highly Cited Ideas in System Codesign and Synthesis”,
CODES+ISSS’08, October 19–24, 2008, Atlanta, Georgia, USA)
76.
K.N. Murali
Mohan, Rohini Krishnan, Anshul Kumar and M. Balakrishnan, " A New Divide
and Conquer Method for Achieving High-speed Division in Hardware", Proc.
of VLSI Design/ASPDAC 2002, Bangalore, India, Jan. 2002, pp. 535-540.
77.
Vishal P.
Bhatt, M. Balakrishnan and Anshul Kumar, `` Exploring the Number of Register
Windows in ASIP Synthsis", Proc. of VLSI Design/ASPDAC 2002, Bangalore,
India, Jan. 2002, pp. 233-238.
78.
Manoj Kumar
Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel and M. Balakrishnan,
"Evaluating Register File Size in ASIP Design", Proc. of CODES 2001,
Copenhagen, April 2001, pp. 109-114.
79.
Basant K.
Dwivedi, Jan Hoogerbrugge, Paul Stravers and M. Balakrishnan, "Exploring
Design Space of Parallel Realizations: MPEG-2 Decoder Case Study", Proc.
of CODES 2001, Copenhagen, April 2001, pp. 92-97.
80.
Manoj Kumar
Jain, M. Balakrishnan and Anshul Kumar, ``ASIP Design Methodologies: Survey and
Issues", Proc. of the Intl. Conf. on VLSI Design, Bangalore, India, Jan.
2001, pp. 76-81.
81.
Anupam
Rastogi, M. Balakrishnan and Anshul Kumar, ``Integrating Communication Cost
Estimation in Embedded Systems Design: A PCI Case Study", Proc. of the
Intl. Conf. on VLSI Design, Bangalore, India, Jan. 2001, pp. 23-28.
82.
Vivek
Haldar, Gokul Varadhan, Abhishek Saxena, M. Balakrishnan and Subhashis
Banerjee, ``Design of Embedded Systems for Real-Time Vision", Proc. Indian
Conf. on Computer Vision, Graphics and Image Processing, (ICVGIP'2000),
Bangalore, India, Dec. 2000.
83.
Akshaye
Sama, M. Balakrishnan and J.F.M. Theeuwen, ``Speeding up Power Estimation of
Embedded Software", Proc. of ISLPED, 23-24th July 2000, Italy, pp.
191-196.
84.
Arvind
Rajawat, M. Balakrishnan and Anshul Kumar,``Interface Synthesis : Issues and
Approaches", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press,
Calcutta, India, Jan. 2000, pp.92-97
85.
T. Vinod
Kumar, P. Sharma, M. Balakrishnan and S. Malik, ``Processor Evaluation in an
Embedded Systems Design Environment", Proc. of 13th Intl. Conf. on VLSI
Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.98-103
86.
Aviral
Srivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar and M.
Balakrishnan,``Optimal Hardware/Software Partitioning for Concurrent
Specification using Dynamic Programming", Proc. of 13th Intl. Conf. on
VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.110-113
87.
Ajoy
Chakravarthy and M. Balakrishnan,``Simulation and Modeling of a Multi-cast ATM
Switch", Proc. of the 12th CSI/IEEE Intl. Conf. on VLSI Design, Goa,
India, Jan. 1999, pp.242-247
88.
Rashmi
Goswami, V. Srinivasan and M. Balakrishnan, ``MPEG-2 Video Data Simulator: A
Case Study in Constrained HW-SW Codesign", Proc. of 12th CSI/IEEE Intl.
Conf. on VLSI Design, Goa, India, Jan. 1999, pp. 128-131
89.
S.K. Lodha,
Shashank Gupta, M. Balakrishnan and S. Banerjee,``Real Time Collision Detection
and Avoidance: A Case Study for Design Space Exploration in HW-SW
Codesign'',Proc. of 11th CSI/IEEE
Intl. Conf. on VLSI Design, Chennai, India, Jan. 1998, pp. 97-102
90.
Sitanshu
Jain, M. Balakrishnan, Anshul Kumar
and Shashi Kumar,``Speeding Up Program Execution Using Reconfigurable Hardware
and a Hardware Function Library'',Proc. of
11th CSI/IEEE Intl. Conf. on VLSI Design, Chennai, India, Jan. 1998, pp.
400-405
91.
A.R. Naseer,
M. Balakrishnan and Anshul Kumar, ``Optimal Clock Period for Synthesized Data
Paths'', Proc. of 10th Intl. Conf.
on VLSI Design, Hyderabad, India, Jan. 1997, pp. 134-139.
92.
Gaurav
Agarwal, Nitin Thapar, Kamal Agarwal, M. Balakrishnan and Shashi Kumar, ``A
Novel Reconfigurable Co-processor Architecture'', Proc. of 10th Intl. Conf. on VLSI Design, Hyderabad,
India, Jan. 1997, pp. 370-375
93.
Heman Khanna
and M. Balakrishnan, ``Allocation of FIFO Structures in RTL Data Paths'', Proc.
of 10th Intl. Conf. on VLSI Design,
Hyderabad, India, Jan. 1997, pp. 130-133.
94.
A.R. Naseer,
M. Balakrishnan and Anshul Kumar, ``A Novel Approach to Direct Realization of
RTL Structures using FPGAs'', Proc. of Intl. Workshop on Logic and High Level
Synthesis, Grenoble, France, December 1996
95.
Alok Kumar,
Anshul Kumar and M. Balakrishnan," Heuristic Search based Approach to Scheduling,
Allocation and Binding in Data Path Synthesis", Proc. of 8th CSI/IEEE Intl. Conf. on VLSI Design,
Delhi, India, Jan. 1995, pp. 75-80.
96.
Varshneya,
B.B. Madan and M. Balakrishnan," "Memory Coupled Scalable
Multiprocessors" Proc. of the 1st Workshop on Parallel Processing,
Bangalore, India, Dec. 1994, pp. 424-429.
97.
A.R. Naseer,
M. Balakrishnan and Anshul Kumar, "An Efficient Technique for Mapping RTL
Structures onto FPGAs", Proc. FPL '94, Prague, Czech Republic, Sep. 1994,
LNCS vol-849, pp. 89-110.
98.
Varshneya,
B.B. Madan and M. Balakrishnan," Concurrent Search and Insertion in
K-Dimensional Height Balanced Trees", Proc. of Intl. Parallel Processing
Symposium, Cancun, Mexico, May 1994, pp.883-887.
99.
A.R.Naseer,
M.Balakrishnan and Anshul Kumar, "A Technique for Synthesizing Data Part
Using FPGAs ", Proc. of 2nd IEEE/ACM Intl. Symp. on FPGAs, Berkeley,
California, Feb. 1994.
100.
A.R.Naseer,
M.Balakrishnan and Anshul Kumar, "FAST : FPGA Targeted RTL Structure
Synthesis Technique", Proc. of 7th CSI/IEEE Intl. Conf. on VLSI Design,
Calcutta, India, Jan. 1994, pp.21-24.
101.
M.V. Rao, M.
Balakrishnan and Anshul Kumar, "DESSERT: Design Space Exploration of RT
Level Components", Proc. of 6th CSI/IEEE Intl. Conf. on VLSI Design,
Bombay, India, Jan. 1993, pp. 299-304.
102.
P.P.
Nedungadi, M. Balakrishnan and Anshul Kumar, "Data Path Synthesis with
Global Time Constraint",(Poster Paper) Proc. of 5th CSI/IEEE Intl. Conf.
on VLSI Design, Bangalore, India,
Jan. 1992, pp.322-323.
103.
Alok Kumar,
Anshul Kumar and M. Balakrishnan, " A Novel Integrated Scheduling and
Allocation Algorithm for Data Path Synthesis", Proc. of VLSI Design '91,
IEEE Computer Society Press, New Delhi, Jan. 1991, pp.212-218.
104.
B.L.
Priyadarshan, M. Balakrishnan, Anshul Kumar and G.S. Visweswaran, "SYMCAD
: Synthesis of Microprogrammed Control for Automated VLSI Design", Proc.
of Intl. Workshop of Microprogramming (MICRO-23), Orlando, Florida, Nov. 1990,
pp. 176-182.
105.
M.Balakrishnan
and Anshul Kumar, "A Comparative Study of Techniques for Synthesis of
Optimal Structures from Behavioral Descriptions", Proc. Of VLSI Design,
Bangalore, India, Jan. 1990. (Reprinted in MicroArch, IEEE Technical Committee
on Computer Architecture, Vol. 5, No. 1, April 1990, pp. 2-7.
106.
M.Balakrishnan
and P.Marwedel, "Integrated Scheduling and Binding: A Synthesis Approach
for Design Space Exploration", Proc. of 26th Design Automation Conference,
'89, Las Vegas, Nevada, USA, June 1989 pp.68-74.
Annexure C
List of applicant’s books
or book chapters published
ASSISTECH:
An Accidental Journey into Assistive Technology, M. Balakrishnan, A Journey of
Embedded and Cyber-Physical System (chapter 5), Ed. Jian-Jia Chen, Springer,
ISBN 978-3-030-47486-7, 2020
Majority
Logic: From Algebra to Synthesis
D.
Rajeshwari, K Paul, M Balakrishnan,
Springer, To appear
Architecture
exploration of FPGA based accelerators for bioinformatics applications
BSC Varma, K
Paul, M Balakrishnan, Springer, ISBN: 978-981-10-0589-3 (Print) 978-981-10-0591-6 (Online), 2016
Anshul
Kumar, M. Balakrishnan, Manoj Kumar Jain and Anup Gangwar, ``Customizing
Embedded Processors for Specific Applications'', Recent Trends in Practice and
Theory of Information Technology, Proc. of NRB Seminar, 10-11 January 2005,
NPOL, Cochin, pp. 261-284, ISBN 81-309-0171-4, © DRDO, Publ. Viva Books
Pvt. Ltd.
Annexure D
List of patents held
Following
patents have been awarded
1.
Patent
No.: 327772
Date of Grant: 19.12.2019
Title of invention:
USER TRIGGERED DUO-MODULE DESTINATION IDENTIFICATION SYSTEM FOR THE VISUALLY
CHALLENGED
Patentee: INDIAN
INSTITUTE OF TECHNOLOGY DELHI
Application No.: 1355/DEL/2007
Date of filing:
22/06/2007
Expiration Date:
22/06/2027
Following
patents have been filed and are under review
1.
Multimodal
Interaction System and Method for Visually Impaired, 201611016353, (Along with
IGDTUW), Filing date 10 May 2016, Disclosure date 30th Oct 2016
2.
Multi-modal
Infotainment Device, (1729/DEL/2014, 27th June 2015)
3.
A Compliant
Mechanism for Refreshable Braille Display Using Shape Memory Alloy
(1575/DEL/2015 dated 5th June 2015 and PCT Application No.
PCT/IN2015/050043 dated 8th June 2015)
4.
A Split Grip
Cane Handle Unit With Tactile Feedback For Directed Ranging (388/DEL/2014, 12th
Feb. 2014)
5.
A System for
Generating Refreshable Tactile Text and Graphic (1669/DEL/2012, 31st May 2012 and PCT application No.
PCT/IN2013/000347 dated 31st May 2013)
6.
Cane-Mounted
Waste Above Obstacle Detection & Warning System (1354/DEL/2007, 22nd June
2007)
Trademarks & Design Registrations
1.
SmartCaneTM
: A trademark registered on 18th Feb. 2014 for our Smart Cane device
(application no.: 2680919)
2.
Cane for
Visually Impaired: Design registration on 21st Oct 2013 (application
no.: 257665)
Annexure E
Sponsored Research and other
significant professional activities
I have been
involved in 32 sponsored projects with a total value of approximately Rs. 15.00
crores. I have been PI of 18 of these projects with a total value of approx 10.00
crores. Apart from DST, Meity etc. I have carried out contract research for Wellcome
Trust, Samsung, NRB, DRDO, Intel, Freescale and EADS
The projects
currently under progress are listed below.
Title |
Sponsoring Agency |
Sanctioned Funds
(Rs.) |
Project Start Date |
Project Completion
Date |
Contextual Rendering of Equations for Visually Impaired Persons (With Uni of Birmingham, UK) |
Google USA |
2520000.00 |
1-1-2021 |
31-12-2021 |
Creating Accessible STEM documents (Under SPARC scheme of MHRD) (With Uni of Birmingham, UK) |
Ministry of Human Resource & Development |
5403480.00 |
03-05-2019 |
02-05-2021 |
Indoor Navigation Assistance of Patients in the RP center |
All India Institute of Medical Sciences (AIIMS) |
1806900.00 |
01-11-2018 |
31-10-2019 |
Development of a Suite of Indigenous Assistive Systems and Tools for
the Disabled Community in India(under IMPRINT scheme) (With IIT Madras and IIT Kharagpur) |
Ministry of Human Resource
& Development India |
12120000.00 |
05-06-2017 |
04-06-2020 |
Some of the
recently completed projects include:
1 |
ICT Centre of
Excellence on Tactile Graphics |
M Balakrishnan PVM Rao Prem K Kalra |
MEITY, Govt. of India |
221.00
Lakhs |
Dec 2014
– May 2018 |
2 |
Development of a
Suite of Indigenous Assistive Systems and Tools for the Disabled Community in
India |
M Balakrishnan |
MHRD, (under IMPRINT scheme), MHRD |
121.20
Lakhs |
June 2017
– June 2020 |
3 |
Indian Sign Language
App for Hearing Impaired |
M Balakrishnan Prem Kalra |
Min. of Social Justice &
Empowerment, Govt. of India |
1.92 Lakhs |
Jan 2017
– Jan 2018 |
4 |
Collaboration
with Indiana University in Tactile Graphics |
PVM Rao M Balakrishnan |
SOIC, IUPUI, USA |
6.40 Lakhs |
Aug 2017
– Aug 2018 |
5 |
On Board Phase 2:
Design, Implementation and Testing of Improved Version Based on Feedback from
the Pilot Trial , DST, Govt. of India |
M Balakrishnan PVM Rao |
DST -
TIDE, Govt of India |
46.12
Lakhs |
Mar 2017
– Mar 2018 |
6 |
Affordable
Refreshable Braille Displays based on Shape Memory Actuation, Wellcome Trust,
UK |
M Balakrishnan PVM Rao (Dipendra Manocha – Saksham Sashi Kumar – Phoenix Medical) |
WELLCOME
TRUST, UK |
618 Lakhs (approx.) (all 4 partners together) |
Apr. 2014
– June 2018 |
7 |
Smart
Cane- Development Course for National and International dissemination |
M Balakrishnan PVM Rao |
WELLCOME
TRUST, UK |
75.00
Lakhs |
Apr 2014
– Oct 2017 |
8 |
Development
of Open source screen reading software NVDA and enhancement with Indian Languages |
M Balakrishnan |
Centre of Internet & Society |
30.40
Lakhs |
Feb 2013
– Mar 2017 |
9 |
INALSI:
Indoor Navigarion with Access to Location
Specific Information |
M Balakrishnan Kolin Paul |
Samsung,
India |
25.00
Lakhs |
Nov 2013
– June 2015 |
10 |
Development
of a Low-cost Electronic Braille Display for the Visually Impaired |
PVM Rao M Balakrishnan |
DST -
TIDE, Govt of India |
38.00
Lakhs |
Sep 2013
– Mar. 2016 |
11 |
OnBoard: Assistive Device for Public Bus Access
for the Visually Impaired |
M Balakrishnan PVM Rao |
DST - TIDE, Govt of India |
35.00
Lakhs |
Sep. 2013
– June 2015 |
12 |
ePSD: Electronic Personal Safety Device |
M Balakrishnan Kolin Paul |
DEITY,
Govt. of India |
48.00
Lakhs |
Nov. 2013
– Mar 2015 |
13 |
Development
of Smart Cane - An Affordable knee-above obstacle detection and warning
system for the visually impaired |
M Balakrishnan PVM Rao Kolin Paul (Dipendra Manocha – Saksham Sashi Kumar – Phoenix Medical) |
WELLCOME
TRUST, UK |
137 Lakhs (approx.) (Total 291
Lakhs) |
Dec. 2010
– Apr. 2014 |
Apart from these sponsored projects, I
have
undertaken 21 consultancies with a total approximate value of Rs. 117 lakhs.
These include consulting projects from globally leading companies in EDA and
VLSI like Synplicity, Sequence Design, ST Microelectronics etc. Other
consultancy projects include embedded product development for Indian industry,
Govt. bodies on system related issues and education related consultancies. Because
of current preoccupation with projects for the visually impaired I do not
undertake any consultancy projects currently.
The SmartCaneTM (Project no 7
& 13 sponsored by Wellcome Trust, UK) that resulted in technology transfer
to Phoenix Medical Systems, Chennai has resulted in royalty income to IIT Delhi
in excess of Rs 1.00 crore
Annexure F
PhD and Other Research Student
Project Guidance
Ph.D. Currently registered:
* Vikas Upadhyay, Ph.D. (2018- )(anz188059@cse.iitd.ac.in)
Co-supervisor: Rohan Paul
Topic: FPGA accelerators for computer
vision applications
*Shikha Goel, Ph.D.
(2018- )(anz162212@cse.iitd.ac.in)
Co-supervisor: Rijurekha Sen
Topic: FPGA accelerators for computer
vision applications
*Akashdeep Bansal. Ph.D.(2016-) (anz168049@cse.iitd.ac.in)
Co-supervisor: Volker Sorge (University of Birmingham)
Topic: Reading assistant for visually
impaired (RAVI)
*Anupam Sobti, PhD. (2016 - ) (anz158497@cse.iitd.ac.in)
Co-supervisor: Chetan Arora
Topic: Multi-sensors and DNN based
vision algorithms
Thesis
Submitted
*Solomon Abera Bekele, Ph.D. (2014- 2020) (csz148241@cse.iitd.ac.in)
Co-supervisor: Anshul Kumar
Topic: Resource Contention Aware
Performance and Power Optimization in
Chip Multiprocessors
Ph.D.
Completed:
*Rajesh Kedia, Ph.D. (2015- 2020)
(csz148383@cse.iitd.ac.in)
Co-supervisor: Kolin Paul
Topic: A framework for designing context-aware
adaptive embedded Systems
*Richa Gupta, Ph.D. (2015- 2020)(anz148356@cse.iitd.ac.in)
Co-supervisors: P.V.M. Rao, Steven Mannheimer (IUPUI, Indianapolis)
Topic: Understanding tactile perception for design of effective tactile
graphics
*Piyush
Chanana, Ph.D. (2012- 2020) (anz128203@cse.iitd.ernet.in)
Co-supervisor: PVM Rao
Topic: Study of independent
travel needs of persons with blindness and assistive technology solutions
Current affiliation: Raised Lines Foundation, IIT Delhi
Start-up
*Gayathri
Ananthanarayanan, Ph.D. (2011- 2017) (gayathri@cse.iitd.ernet.in)
Co-supervisor: Smruti Sarangi
Topic: Power estimation for systems based on multi-core processors
Current affiliation: IIT Dharwad
*Arun Parekh, Ph.D. (2009-2016) (aparakh@cse.iitd.ernet.in,
Co-supervisor: Kolin Paul
Topic: Performance Estimation and Mapping of Applications onto
GPUs
Current
affiliation: SGSIT Indore
* Rajeswari, Ph.D. (2008-2015)(drajeswari@cse.iitd.ernet.in)
Co-supervisor: Kolin Paul
Title: Novel Architectures and Synthesis Methods for Quantum-dot
Cellular Automata
*Mansureh Shahraki, Ph.D. (2010- 2015) (mansureh@cse.iitd.ernet.in)
Co-supervisor: Kolin Paul
Title: Application Mapping onto Reconfigurable Coarse-Grained
Arrays
Current affiliation: INRIA, CAIRN,
France
*Sharat Chandra Varma, Ph.D. (2008- 2014) (varma@cse.iitd.ac.in)
Co-supervisor: Kolin Paul
Title: Architecture
Exploration of FPGA Based Accelerators for Bioinformatics Applications,
Current Affliation: Lecturer, University
of Belfast
* Lava Bhargava, Ph.D. (2005- 2013)(lava@cse.iitd.ernet.in)
Co-supervisor: Ranjan Bose (EE)
Title: Energy Estimation and Modeling of LDPC Decoders
Current affiliation: Professor, NIT Jaipur
* Sonali Chauhan, Ph.D. 2010, (sonali@cse.iitd.ernet.in)
Co-supervisor: Ranjan Bose(EE)
Title: An Integrated Framework for Energy Optimization of Wireless
Sensor Nodes
Current affiliation: Associate Professor, EE Deptt., IIT Gauhati
* Aryabartta Sahu, Ph.D., 2010, (asahu@cse.iitd.ernet.in)
Co-supervisor: Preeti Ranjan Panda
Title: Evaluation and Mapping of Applications on Heterogeneous
Multiprocessor Systems
Current affiliation: Associate Professor, CSE Deptt., IIT
Gauhati
* Anup Gangwar, Ph.D. 2005, (anup@cse.iitd.ac.in)
Co-supervisor: Anshul Kumar
Title: Performance Driven Synthesis of Application Specific
Clustered VLIW Processors
Current affiliation: ARM, Austin, Texas
* Basant Diwedi, Ph.D. 2005, (basant@calypto.com)
Co-supervisor: Anshul Kumar
Title: Synthesizing Application Specific Multiprocessor
Architectures for Process Networks
Current affiliation: Synopsys, Bangalore
* Rajeshwari Banakar, Ph.D. 2003, (banakar@cse.iitd.ernet.in)
Co-supervisor: Ranjan Bose(EE)
Title: A Low Power Design Methodology for Turbo Encoder and
Decoder
Current affiliation: Professor, & HoD, E&C Department, BVB
Engineering College, Hubli
* Manoj Kr. Jain, Ph.D. 2003, (manoj@cse.iitd.ernet.in)
Co-supervisor: Anshul Kumar
Title: Exploring Register File Size and Memory Configuration in
ASIP Synthesis
Current affiliation: Professor, Udaipur University, Udaipur
* A.R. Naseer, Ph.D. 1995, (arnaseer@kfupm.edu.sa)
Co-supervisor: Anshul Kumar
Title: Realization of Synthesized RTL Structures on LUT based
FPGAs
Current affiliation: Inha
University, Tashkent
* Atul Varshneya, Ph.D. 1995,
Co-supervisor: B.B. Madan
Title: Parallel Dictionary Operations: Algorithms and
Architectures
Current affiliation: Tavant, California
Ph.D. Completed
(Closely associated with):
* Anant Vishnoi, Ph.D. (2003- )(anant@cse.iitd.ernet.in)
Supervisor: Preeti Ranjan Panda
Title: Cache Data Compression: Algorithms and Hardware
Implementation
Current affiliation: Assistant Professor, IIT Ropar
* Alok Kumar, Ph.D. 1993 (alokk@coware.com)
Supervisor: Anshul Kumar
Title: A Versatile Data Path Synthesis Approach based on Heuristic
Search
MS(R) in
progress:
*Radhika
Dharwadkar (2014 -) (siy147530@cse.iitd.ac.in)
System
level design and modeling of MAVI
MS(R)
Completed:
*Suman
Muralikrishna (2015 -) (siy157524@cse.iitd.ac.in)
Low
power design of Refreshable Braille Display
* C.P. Joshi, M.S. 2003, (chandra.p.joshi@intel.com)
Co-supervisor: Anshul Kumar
Title: Communication Modeling and Performance Analysis of Embedded
Systems
* Piyush Gupta, M.S. 2003, (piyush_g@yahoo.com)
Co-supervisor: Sanjeev Kapoor
Title: Automating Functional Partitioning Over Heterogenenous
Platforms for Design of Embedded Systems
* M. Anand, M.S. 1998, (anand@exact-solutions.com)
Co-supervisor: Sanjiv Kapoor
Title: Hardware/Software Partitioning between Microprocessor and
Reconfigurable Hardware
Apart from these supervised 124
M.Tech. and 84 B.Tech projects (upto
July 2019)
Annexure G
Associated Start-Ups
I have been
a founding member/initiated three start-ups
Name |
Activity |
Remarks |
KritiKal
Solutions https://kritikalsolutions.com/ |
Design
services and products in the space of embedded systems and vision
applications |
Along with
four other faculty members and seven graduates of IIT Delhi formed an
embedded and vision design services company in 2002 |
Vehant
Technologies https://www.vehant.com/ |
Vision and
Image Processing products company |
Along with
another investor, KSPL formed
KritiKal Secure Scan in 2005/06. Later it was renamed as Vehant Technologies |
Raised
Lines Foundation http://www.raisedlines.org/ |
Tactile
books for the visually impaired. Primary objective is to facilitate inclusion
of visually impaired in STEM higher education with affordable tactile books |
Along with
two other founders, formed a section 8 (non-profit) company in 2018 based on
the know-how developed in the project “Centre of Excellence in Tactile
Graphics” |
Annexure H
Technology
Transfers
My group has
been responsible for developing products/solutions resulting in six technology
transfers
Name |
Transferred to |
Function |
Impact |
FPGA
Education Kit |
VPL
Infotech, NOIDA https://vplinf.com/ |
Educational
trainer kit for FPGAs |
500+ units
were sold in 60+ Institutions |
SmartCaneTM |
Phoenix
Medical Systems https://www.phoenixmedicalsystems.com/ |
Mobility
aid for visually impaired |
80,000+
devices sold in India and 20+ other countries |
DotBookTM |
KritiKal
Solutions https://kritikalsolutions.com/ |
Refreshable
Braille laptop |
Small
volume production had started |
SMA based
Braille Cell Module |
Phoenix
Medical Systems https://www.phoenixmedicalsystems.com/ |
Refreshable
Braille cell module for DotBookTM |
|
OnBoardTM |
KritiKal
Solutions https://kritikalsolutions.com/ |
Aid for
visually impaired to board public buses |
Tested
with pilots in 25 BEST buses and 20 Orange cluster buses in Mumbai and Delhi
respectively |
Know-how
for Tactile Diagram Design and Production |
Raised
Lines Foundation http://www.raisedlines.org/ |
Tactile
books for the visually impaired |
Already 1,50,000
tactile diagrams, 30+ titles and 6400+ tactile books delivered |
Annexure I
Other
Professional Activities
§ Associate Editor, ACM TECS (2016
- )
§ Associate Editor, IEEE Embedded Systems Letters
(ESL)(2013-2016)
§ Fellow, INAE
§ Senior Member, IEEE
§ Senior Member, ACM
§ Lectures at Philips Research,
Philips Semiconductors, Wipro, Cadence Design Systems. ARM and numerous universities
and research laboratories in Germany, France, The Netherlands, USA, Malaysia,
Korea, Qatar, Australia, Nepal and Singapore
§ Tutorials at two VLSI Design
Conferences and two VDAT Conferences
§ Keynotes at more than forty
conferences
§ Member of ACM DSP, New York
(selection of ACM Distinguished Speaker Awardees) (2011-2014)
§ Eureka Rajya Sabha TV Broadcast
(6 Jan 2018)
§ Reviewer for IEEE TCAD, ACM
TODAES and many other journals
§ Technical Program Chair of VLSI
Design 1995 and 2003
§ Organizing Chair FPT 2011, (Dec
2011)
§ TPC of VLSI, ISLPED, ASP-DAC,
ED&TC, ISSS, CODES, DSD, ESTiMedia
§ Chairman, Delhi-NCR ACM Chapter
§ Chairperson/Member of numerous
PRS&G committees of DEITY, MCIT
§ Chairperson for two years of MSJE
committee for selection of National Awardees
Annexure J
Education and Research Management:
Key Initiatives and Contributions
J1: Role
of Deputy Director (Strategy & Planning) (20016-19)
Starting from 1st July 2016 to 31st Oct
2019 I was the Deputy Director (Strategy & Planning) at IIT Delhi. In this
period I not only worked very closely with the Director (Prof. Ramgopal Rao) to
implement the Institute’s agenda but also a played a key role in
initiating as well as implementing many significant changes in academic
structures and Institute management. Some key activities where I played a
critical role include the following.
i.
I directed the preparation of the IIT Delhi’s Institution of Eminence proposal that was
accepted by the committee and IIT Delhi became one of the first three public
Institutions to be given IoE status
ii.
Steps needed to achieve many of the goals of IoE including
recruitment of International students and faculty
iii.
Played a key role in many of the initiatives to make our
academic offerings modern -Setting up SIRE (School of Inter-disciplinary
Research), School of Public Policy, School of Artificial Intelligence, Department
of Materials Science & Engineering, Department of Design and major
Restructuring of two existing centres (CART for electric vehicles and SENSE for
sensors and cyber-physical systems)
iv.
Setting up of the JATC – a DRDO centre
v.
Building strong partnerships with Institutions in the
neighborhood including AIIMS and JNU
vi.
First two joint PhD programs with University of Queensland,
Australia and NCTU, Taiwan
vii.
Operationalization of the I-TEC, IIT Delhi’s Sonepat
campus
viii.
Expansion of Central Research Facility (CRF) in the campus as
well as in Sonepat
ix.
Expansion of the incubation program in IIT Delhi
x.
Handling all issues related to student strength increase from
EWS (economically weaker section) quota and gender balance quota
xi.
Review of internal revenue generation (IRG) due to shift from
grants to HEFA loan by the Govt for asset creation and steps like change in fee
structure and hostel seat rent to increase IRG
J2: Key
Initiatives/contributions in previous academic leadership roles (2001-16)
1. Contributing to Enhancing
the Research Profile of IIT Delhi: IITs have established an image world wide of a quality
undergraduate institution though its PG to UG ratio at 3:2 is higher than most
other research universities in the world,.
As Dean Post Graduates Studies & Research, I was actively engaged in
policies and programs to do the image makeover. All these were geared towards
increasing the number and quality of doctoral students and also projecting the
Institute beyond its undergraduate education. The number of PhD students increased
from approximately 780 to nearly 1350 in my tenure as Dean(PGSR) i.e. from 2006
to 2009. Some significant initiatives are listed below.
a.
Significant
policy changes piloted included facilitating enrolment of project staff in
masters and PhD programs, easy changeover from masters to PhD and provision of
admission of our UG students to PG programs with advance standing.
b.
For
projecting the Institute research, an Open House on the fourth Saturday of
April was started for public demonstration of research projects, a PG website
listing major achievements of our PG students (www.iitd.ac.in/pg),
international conference participation as well as thesis presentations
Institute wide. Working with industry sponsors as well as alumni donors for
strengthening the PG programs and give it higher visibility. As part of this
initiative, started celebration of National Science day (28th Feb.)
as a research Scholars day where selected PhD students from different
departments, present their work in a poster session as well as seminars.
c.
Towards the
same end with a view to creating a unique space for IIT Delhi among the NCR
(National Capital Region) industries, a professional candidate registration
scheme which permits engineers from industries to register for regular courses
in the Institute to upgrade their knowledge and skills has been started. To
encourage participation by eliminating travel time, a few select courses were
also being taken to industry sites through video conferencing.
2.
Scaling up Research and Quality Education: There has been a major
expansion of technical education in the country but most of the faculty joining
these new Institutions though expected to do PhD for career growth but has no
exposure to quality research. With a view to address this, took initiative to
introduce the summer faculty research fellowship program that enables teachers
from different colleges to spend time in summer associated with the IIT Delhi faculty
in the domain of their research interest. Started in summer of 2008, at present
IIT Delhi hosts nearly 150 faculty members each year and a significant fraction
of them start their research at IIT Delhi or elsewhere soon after that
3. Innovative Experiments in
Education/Research: I have been
in the forefront of a majority of innovative changes that have happened in IIT
Delhi in the last 15 years. This includes dual degree program, 1-credit module
research courses, member of the UG curriculum committee that was adopted in
2003, formalizing teaching assistantship functions etc. In addition I would
like to mention two major initiatives to increase global footprint of IIT
Delhi.
a.
A distance
education program across continents (with Ethiopia) has been offered at the
post-graduate level. This was the outcome of a delegation I took to Ethiopia on
the invitation of their education ministry. The program provided instruction
through 2-way audio-video links and a limited one-week interaction period per
semester. Nine different programs from four different Engineering disciplines were
completed. Nearly 500 Ethiopian Engg teachers (that constitute a significant
fraction of teachers in technical Institutions in Ethiopia) have now been
trained by IIT Delhi. This involved more than 80 visits involving nearly 50
faculty members from 5 different departments. IIT Delhi is receiving large
number of PhD applications from Ethiopia which can be directly attributed to
this initiative. This is perhaps a beginning to make IIT Delhi a truly
international institution. This could have been one of the largest post graduate
distance education programs in the world.
b.
On the
invitation of the education ministry of Govt. of Mauritius, I took a 6-member
delegation to Mauritius to study the feasibility of setting up an IIT like
Institution. The study produced a unique model of a research based IIT Delhi academy
transforming in 5 years to an IIT like Institution supporting both UG education
and research. The feasibility study was accepted by the Mauritius Govt. IIT
Delhi and MRC then signed an MoU for setting up an IITRA (International
Institute of Technology Research Academy) at Mauritius which was expected to
start functioning from summer of 2014. We even recruited a few PhD students and
faculty members. This would have brought a unique visibility to IIT Delhi
especially in Africa and can have a major impact in our research capability
buildup. Unfortunately the project had to be shelved as the new Indian Government
formed in 2014 was the opinion that IIT statutes did not permit establishment
of a research academy abroad by IITs.
Annexure K
Key Initiatives and Contributions in
Embedded/VLSI/EDA/CS Domains
1.
Establishing a Centre for
Embedded Assistive Technologies for the Disabled (AssisTech): Esablished a
centre that is dedicated to development of embedded assistive devices for the
disabled – main focus has been mobility and education of visually
impaired. Initial success was achieved by building prototypes of “Smart
Cane” and “User Triggered Bus Identification System”.
“Smart Cane” technology has already been transferred to industry
with the “Bus Identification System” ready for technology transfer.
SmartCaneTM has been under production for more than 5 years and has
more than 80000 users in India and twenty two other countries. This started by mainly involving undergraduate
students from CSE, EE and Mechanical Engg and is aimed towards developing and creating
affordable solutions for the physically impaired people in the developing
world. (assistech.iitd.ac.in). Another prestigious project
on Refreshable Braille Display sponsored by Wellcome Trust (Grant amount >
USD 1 million) has been completed and products for sampling under the brand
name DotBookTM have been launched. A Centre of Excellence in Tactile
Graphics funded by MEITY has successfully created a process and technology for
end-to-end production of affordable tactile diagrams (coetg.iitd.ac.in).
This know-how has been used to incubate Raised Lines Foundation (http://raisedlines.org/) a
section 8 non-profit company. I initiated a major conference in Assistive
Technology named EMPOWER 2018 (assistech.iitd.ernet.in/empower2018/) in
October 2018 which saw AT researchers and users from all over the country and
some globally renowned AT experts as speakers. Based on its success we followed
it up with EMPOWER 2019 in October 2019 (assistech.iitd.ernet.in/empower2019/). This
year it would be organized by IIIT Bangalore. My work in AT space has been
recognized through three national awards (two by DST and one by MSJE) and the
ACM Eugene L Lawler award (2019) in the last five years.
2. M.Tech. VDTT Program: Key person in initiating the
first fully industry sponsored M.Tech. programme in VLSI Design, Tools and
Technology. Almost all the major VLSI and EDA companies have sponsored students
to this program at one time or other.
This has emerged as an innovative nationally recognized post graduate program
attracting the very best students and setting a model of sponsorship as well as
successful collaboration CS and EE Departments. A number of students have taken
to research with strengths in both disciplines and are sure to emerge as
leaders in this domain in the future.
3. Pioneered introduction of FPGAs
in UG curriculum: Recognizing
its potential early on i.e. in early 90’s, I have worked constantly
towards introducing FPGAs in the UG curriculum. First it was in the form of
project work and then it became part of the digital lab in mid-90s and today
second year students in CS and EE go through a digital systems design
experience around FPGAs. In this process developed an educational kit and
transferred know-how to a micro-controller kit manufacturer for production;
developed a set of experiments and conducted short workshops for teachers and
6-week long workshop for students from other engineering colleges.
4. First Faculty-Student led Startup
at IIT Delhi: IIT Delhi
had an incubator with few takers from the Institute community. With the CS
graduates of 2002, facilitated the first joint faculty-student led startup
named ”KritiKal Solutions Pvt. Ltd.” (www.kritikalsolutions.com). KritiKal emerged as a trend
setter motivating more than 15 such startups in the campus. Kritikal Solutions
acts as a design house in the area of Embedded Systems and Computer Vision and
employs around 150 people now. Another company named named Vehant Technologies
(formerly called KritiKal Secure Scan) was incubated which has camera based
security products. I was a founder/mentor of KritiKal Solutions and spent half
of my sabbatical time in 2004-2005 working with the startup; a trend which has
been followed by a number of faculty members since in IIT Delhi.
5. Establishing the Best Known
Embedded Systems Research Group in India: IIT Delhi has
the strongest embedded systems research group with five faculty members and
nearly twenty active research students. This has been possible with myself
working closely with Prof Anshul Kumar in the period from 1990 to 2010. Even at
that time the research group has reached more than half a million dollar in
research funding from Govt. as well as R&D units of industry in India and
abroad. The group started regular workshops in system level design which has
now emerged as one track in the VLSI design conference as Embedded Systems
Conference. Finally this resulted in attracting three more highly qualified faculty
members to the Department.
6. Significant Member of VLSI Design
Conference: VLSI design
conference has emerged as a key event attracting technical papers from India
and abroad, a vibrant exhibition and major networking event at one time was
attracting more than 1000 delegates. In the period from 1990 to 2016, I have
continuously worked to promote the event and participated in many capacities. I
have been the technical program chair for the 1995 and 2004 events, proposed
and initiated the design contest, been fellowship chair etc. I initiated the
Embedded Systems conference which runs as a special track in the conference.
Was a member of the steering committee for nearly two decades and participated
actively in giving direction to the society. Presented papers in most of the
years, given tutorial twice and been on the panel discussions a number of
times. The platform provided by VLSI design and its sister event VDAT, has
played a significant role in the growth of industry, education as well as
research in VLSI in India.
7. Founding Member of ACM India: In 2010, started the ACM India section along with seven other
founding members. It is already growing and making an impact on technical
activities in CS in India.
Annexure L
Academic Planning at Satya Bharti
Institute of Technology
(2 Jan 2020 – 30 Sep 2020)
1.
Background: Satya Bharti Institute of Technology was
being founded by Satya Bharti Foundation (SBF) which itself was promoted by the
founders of Bharti Enterprises. They were already involved heavily in school
education of large number of students from economically and socially weaker
sections of the society through Bharti Foundation (BF). A key objective of the SBF
was to provide high quality technical education to a significant number of
students from economically weak as well as rural/semi-urban background. The
founders applied for “Institution of Eminence” (IoE) status and
were one of the two private Institutions that received Letter of Intent as a
Greenfield IoE. This also meant that Satya Bharti was to be a
multi-disciplinary Institution with 10,000 students, 10:1 faculty–student
ratio and to be ranked within 500 globally in 10 years. The plan was to acquire
land (in Mohali), completely build significant part of the campus and start the
academic programs in July/August 2022.
2.
My role: I was appointed as the founding Vice
Chancellor in late November 2019 and I joined on 2nd Jan 2020 on a 5
year contract. My responsibility was to completely develop both academic and
research programs and that included strategy for faculty recruitment, student
admission etc. I needed to work with AGB (Academic governing body) and CTM
(Core team) which consisted of academicians, entrepreneurs and legal/finance
managers from both within India and abroad. On the positive side, I had more
than 30 months available to plan and roll out the academic programs. In the
nine months I was there, I built a small support team (4 members) and focused
on key initiatives/differentiators to address the more difficult aspects of
building a quality Institution quickly.
3.
Academic programs: Some key decisions are listed below
i.
For the undergraduate program we planned to create an eco-system of
innovation and to achieve that we added Design and Management programs to CS
and EE programs mentioned in the IoE application. Idea was to encourage
students to form inter-disciplinary groups and think about product/process
design. Curriculum itself would have flexibility to trade-off course credits
with additional project credits and that can be done through 2nd to
4th year. Academic advisory committees for Management and Design
programs were constituted and detailed recommendations as to the structure/nature
of these programs (not detailed curriculum) were evolved.
ii.
An alternative option to in-campus education was formulated. Students can
take up an option where he/she would be off-campus each year starting second
year for 10 months doing Internship along with 10 credits of course work per
semester online. Student would come to the campus during summer for those
courses and laboratories that cannot be effectively offered online. This would
enable students who cannot afford full-time college education even with tuition
waiver to pursue studies in the “earn while you learn” mode. Of
course it would help even other students undergoing this alternative program
with better employment opportunities.
iii.
One key consideration in UG program design was that though the students
may come assigned to pursue education in some discipline but would have
complete flexibility in changing their “major” within the first two
years based on their interest and aptitude. First year courses would be
designed keeping in view this requirement – students should have an
opportunity to understand his/her own strengths and interest.
iv.
PhD programs were to start almost simultaneously with the UG programs as
without that attracting faculty who are active researchers would be hard.
Registration of students from industry for PhD program was to be promoted by
removing the residency requirement and defining a different IPR ownership
policy for the industry sponsored students. PhD fellowships were to be bundled
to faculty professional grants making faculty stakeholders in attracting
students. This was expected to encourage them to make their research more
visible.
v.
PG programs were to be mainly online programs and would start only after Satya
Bharti had sufficient number of faculty in a particular sub-discipline for
starting the Master’s programs.
4.
Student admission: One key differentiator was at Satya
Bharti we wanted to make School recommendations/nominations an integral part of
the school admission process. Engaging with schools and school teachers was
considered desirable rather than adopting an existing or a new entrance
examination solely for admissions. Plan was to seek nominations from schools BF
has already been working with for many years. These were all state government
schools mainly in the rural/semi-urban area and typically gets students who are
poor and can’t afford private school education. Bring the nominated
students to a one week or two weeks Science camp and select from them after
observing their performance and preparedness. Recognize and reward those
schools and school teachers whose alumni do well in Satya Bharti. These
students were to be provided free education and in some cases free boarding and
lodging as well (need based). Over a period of time, this would make these
Schools and School teachers’ key stakeholders in Satya Bharti.
5.
Faculty recruitment: Recruiting quality faculty with strong
research record established through
their education and publications is the most difficult part in building any
quality Institution. A number of initiatives were planned to attract top
quality faculty.
i.
Organize six 2-week research workshops with upto 8 top quality speakers
(5/6 from abroad and 2/3 from India) and 30 invited participants who are all
senior PhD students/post-docs working in leading research groups across the
world. This was clearly an exercise to make Satya Bharti name visible across
the relevant research communities in an accelerated manner. Note in each
workshop we were planning to invite 25 participants from abroad and 5 from
India and fully pay for their travel, boarding and lodging. Even if they do not
themselves apply for a faculty position, other students working in their
research groups would come to know about Satya Bharti. An extensive list of
active research groups in key research areas was prepared to kick-start this
activity.
ii.
It is very hard to recruit
senior faculty who are active researchers. To be able to attract senior
faculty, research centres with chair positions was defined. These chairs would
not only be provided with space as well as funding for equipment and research
scholars to setup their research centres. Further, they would also have a
direct responsibility of recruiting 6 to 8 faculty in their research domain.
The expectation of senior faculty working in top Institutions in India who are
struggling to get support for starting their research groups or those wanting
to return from abroad in mid-career may find this offer attractive. These
chairs were to be advertised in many International professional magazines and
e-groups.
iii.
To attract adjunct faculty from industry as well as other independent professionals’
attractive terms of engagement were evolved. They need to commit to only
2-weeks in a year in the campus and would be able to define and supervise student
projects at all levels (including PhD) as well as mentor students and start-ups
independently.
iv.
Possibility of joint appointment with industry or another Institution
with time splitting between the two organizations was defined. This would not
only significantly enhance the compensation package to a new recruit but also
provide access to industry problems and data for research. Even in this short
period we had some success in getting support letter from a leading industry
for such joint appointment.
6.
Academic calendar: A unique academic calendar consisting of
two 4-month semesters, one 2-month summer term and four 2-week short terms was
defined. The idea was such a calendar would promote a strong visitor program
both within India and abroad. Being able to invite established academicians or
professionals can not only result in high quality education but also can
accelerate visibility to attract full-time faculty.
7.
Status: The academics plans were being drawn up with a view to start the programs
in July/August 2022. Unfortunately promoters were having difficulty in land
acquisition as a large campus for housing not only academic buildings but also
the students and faculty was being planned. Covid-19 pandemic made founders to think
afresh – should we really go towards a full brick-and-mortar campus for
all the students or have a new paradigm that provides for a small residential campus
with more students studying online. As the IoE status meant a strong emphasis
on the physical infrastructure, this may not have been feasible. Finally in
late September, founders decided to close the project and tie up with another
upcoming Institution (Plaksha University in Mohali) with a similar charter for
sponsoring economically weak students.